JEDEC STANDARD Board Level Drop Test Method of Components for Handheld Electronic Products JESDB JULY JEDEC SOLID. The reliability of this package has been studied by employing the JEDEC JESDB standard drop test. In this paper, the JEDEC B-condition is applied to. The need for RoHS compliant boards coupled with the demand for reliable electronics has resulted in the development of the JEDEC Standard JESD B to.

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The electrical resistance of each net shall be measured in-situ during each drop and all failures shall be logged. The overall board size shall be mm X 77 mm that can accommodate up to 15 components of same type in a 3 row by 5 column format. It should be noted, however, that any additional mass will add significant dynamic weight to the board and may alter its dynamic response.

The area of the board in the length direction outside of components shall be restricted for labeling, through holes, edge fingers, and any other fixtures, if needed. All components used for this testing must be daisy-chained.

There shall be four holes on the board to be used for mounting board on drop test fixture. Therefore, it is recommended that this characterization should jesd2 be done on a jsed22 board. All routing and traces within and just outside the component footprint shall be done on layer 2 and layer 8 for area array packages and layer 1 and layer 8 for perimeter leaded packages. Since components with body sizes larger than 15 mm x 15 mm in size are not used in these applications, the maximum size of the component body covered in this standard is 15 mm x 15 mm.

The free-fall drop height of the drop table needed to attain the prescribed peak acceleration and pulse duration. These handheld electronic products are more prone to being dropped during their useful service life because of their size and weight.

The failure is a strong function of the combination of the board design, construction, material, thickness, and surface finish; interconnect material and standoff height; and component size. Although daisy-chain nets will typically not require plated though holes PTH other than those required for manual probe pads and connectors, the test board shall contain PTH in the component region 1.

The maximum acceleration during the dynamic motion of the test apparatus. The first event of intermittent discontinuity as defined above followed by 3 additional such events during 5 subsequent drops.

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The screw shall be tightened until the shoulder of the screw bottoms out against the standoff. The capture pad diameter shall be at least microns. Additional accelerometer may also be mounted on the board assembly at or close to one of the support locations to ensure that the uesd22 pulse to the base plate is transmitted to the PCB without any distortion.

This test method is not meant to address the drop test methods required to simulate shipping and handling related shock of electronic subassemblies. The primary driver of these failures is excessive flexing of circuit board due to input acceleration to the board created from dropping the handheld electronic product.

I recommend changes to the following: For example, a 9 x 9 pad array can jesd2 designed to accommodate suitably designed daisy chain components with 8 x 8, 7 x 7, 8 x 9, or any other ball array combination. The locations of these holes are shown in Figure 1. There shall be 20 plated through holes per square centimeter in the component region.

In case of rectangular components, the longer side of the component should be parallel to the longer side of the board when mounted.

All cables shall be cleared from the drop path. Therefore, this standard requires that the board shall be horizontal in orientation with components facing in downward direction during the test.

A printed circuit board assembly with components mounted on only one side of the board double-sided PCB assembly: The modulus and Tg of the dielectric materials shall be specified. This flexing of the board causes relative motion between the board and the components mounted on it, resulting in component, interconnects, or board failures. The board shall still be designed as double-sided with footprint of similar sized components on each side. This shall be accomplished by designing double sided boards with mirror component footprint on each side top and bottom of the board.

A trace width of microns shall be used for all traces outside of component region. Drop testing on other board orientation is not required but may be performed if deemed necessary.


The glass transition temperature, Tg, of each dielectric material as well as of the composite board shall be oC or greater. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally.


During the test, jdsd22 shock pulse shall be measured for each drop to ensure that input pulse remains within the specified tolerance. The maximum number of drops shall be 30 irrespective of kesd22 or double-sided assembly.

The component bb111, dimensions, and assembly processes shall be representative of typical production device. By downloading this file the individual agrees not to charge for or resell the resulting material.

The comparability between different test sites, data acquisition methods, and board manufacturers has not been fully demonstrated by existing data. The maximum component size shall be 15 mm in length or width and there shall be at least 5 and 8 mm gap between the components in x- and y-direction, respectively.

This dropping event can not only cause mechanical failures in the housing of ejsd22 device but also create electrical failures in the printed circuit board PCB assemblies mounted inside the housing due to transfer of energy through PCB supports.

The drop table shall then be raised to the height specified according to JEDEC condition and dropped on the strike surface while measuring the G level, pulse duration, and pulse shape. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. Similarly, a larger group containing components in Group B and D may also exist.

The information included in JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement.

Smaller clearance can be used as long as it does not cause any solder mask encroachment on pads jesd222 to misregistration. Although it is recommended that jezd22 characterization be performed for previously untested components, this may not be required if such characterization data is available for similar sized component. As a result, if the data are to be used for direct comparison of component performance, matching study must first be performed to prove that the data are in fact comparable across different test sites and test conditions.

Therefore, options are provided for mounting just 1 or 5 components on the board using the following locations: